Epson PowerLite 4100 - Parallel Interface Timing

Operator's Guide C-7
PARALLEL INTERFACE TIMING
The illustration that follows shows the sequence for parallel data
transmission.
DATA 1
through
DATA 8
STROBE
1
3
2
4
6
8
ACKNLG
BUSY
7
5
Parallel Interface Timing
AB0-AR
1. Data set-up time (1 µs, minimum)
2. STROBE* pulse width (1 µs, minimum)
3. Data hold time (1 µs, minimum)
4. STROBE* to BUSY delay (100 ns, typical)
5. BUSY length (variable; 35 µs, typical)
6. BUSY negation to ACKNLG* delay (100 ns, typical)
7. ACKNLG* pulse width (5 µs)
8. ACKNLG* assertion to STROBE* delay (2 µs, minimum)