Epson S1D13706 - Page 272

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Epson Research and Development
Vancouver Design Center
S1D13706 13706CFG Configuration Program
X31B-B-001-03 Issue Date: 01/03/29
BCLK These settings select the clock signal source and divisor
for the bus interface clock (BCLK).
Source The BCLK source is CLKI.
Divide Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the BCLK source to derive
BCLK.
Timing This field shows the actual BCLK frequency used by
the configuration process.
MCLK These settings select the clock signal source and input
clock divisor for the memory clock (MCLK). MCLK
should be set as close to the maximum (50 MHz) as
possible.
Source The MCLK source is BCLK.
Divide Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the MCLK source to
derive MCLK.
This divide ratio should be left at 1:1 unless the
resultant MCLK is greater that 50MHz.
Timing This field shows the actual MCLK frequency used by
the configuration process.