Epson Research and Development
Page 13
Vancouver Design Center
13706CFG Configuration Program S1D13706
Issue Date: 01/03/29 X31B-B-001-03
PWMCLK These controls configure various PWMCLK settings.
The PWMCLK is the internal clock used by the Pulse
Width Modulator for output to the panel.
Enable When this box is checked, the PWMCLK circuitry is
enabled.
Force High The signal PWMOUT is forced high when this box is
checked. PWMOUT is forced low when this box is not
checked and Enable is not checked
Source Selects the PWMCLK source. Possible sources include
CLKI and CLKI2.
Divide Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the PWMCLK source to
derive PWMCLK.
Timing This field shows the actual PWMCLK frequency used
by the configuration process.
Duty Cycle Selects the number of cycles that PWMOUT is high out
of 256 clock periods.
Contrast Voltage Pulse These controls configure various Contrast Voltage
(CV) Pulse settings. The CV Pulse is provided for
panels which support the contrast voltage function.
Enable When this box is checked, the CV Pulse circuitry is
enabled.
Force High The signal CVOUT is forced high when this box is
checked. CVOUT is forced low when this box is not
checked and CVOUT is not enabled.
Source The CV Pulse uses the same source clock as the
PWMCLK.
Divide Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the CVOUT Pulse clock
source to derive the CV Pulse clock frequency.
Timing This field shows the actual CV Pulse frequency used by
the configuration process.
Burst Length The number of pulses generated in a single CV Pulse
burst.
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