9.3 Communication Methods
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99
Standard Event Status Enable Register (SESER)
Setting any bit of the Standard Event Status Enable Register to 1 enables
access to the corresponding bit of the Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable
Register (SESER)
Device-Specific Event Status Register (ESR0)
This instrument provides one event status register for controlling events.
Each event register is an 8-bit register.
When any bit in one of these event status registers enabled by its corresponding
event status enable register is set to 1, the following happens:
• For Event Status Register 0, bit 0 (ESB0) of the Status Byte Register
(STB) is set to 1.
Event Status Register 0 is cleared in the following situations:
• When a
∗CLS command is executed
• When an Event Status Register query (:ESR0?) is executed
• When the instrument is powered on
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
&&&&&&&&
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Logical sum
Standard Event Status Register (SESR)
Standard Event Status Enable Register (SESER)
bit6 bit5 bit4
SRQ
MSS
ESB MAV
Event Status Register 0 (ESR0)
Bit 7 - unused
Bit 6 - unused
Bit 5 - unused
Bit 4 - unused
Bit 3 EOM Test end bit
Bit 2 LFAIL Beyond the comparator lower-limit value
Bit 1 UFAIL Beyond the comparator upper-limit value
Bit 0 PASS Within the comparator range
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