IDT 8A3 Series - DPLL_0.DPLL_LOCK_0; DPLL_0.DPLL_LOCK_1

148©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
DPLL_0.DPLL_LOCK_0
Phase lock threshold.
DPLL_0.DPLL_LOCK_1
Phase lock monitor duration.
DPLL_0.DPLL_HO_CFG Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
HOLDOVER_MODE[2:0] R/W 0 Holdover type configuration.
simple: holds DPLL with latest integrator value
manual: holds DPLL with value from
DPLL_CTRL_n.DPLL_MANUAL_HOLDOVER_VALUE
advanced: holds DPLL with value derived from filtered DPLL frequency history
0 = simple
1 = manual
2 = advanced
Table 182: DPLL_0.DPLL_LOCK_0 Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_0.DPLL_LOCK_0 Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
00Bh PHASE_UNIT[7:6] PHASE_LOCK_MAX_ERROR[5:0]
DPLL_0.DPLL_LOCK_0 Bit Field Descriptions
Bit Field Name Field Type Default Value Description
PHASE_UNIT[7:6] R/W 0 Phase lock threshold unit.
0 = 1 ns
1 = 10 ns
2 = 100 ns
3 = 1 us
PHASE_LOCK_MAX_ERR
OR[5:0]
R/W 0 Phase lock threshold value.
Table 183: DPLL_0.DPLL_LOCK_1 Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_0.DPLL_LOCK_1 Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
00Ch PHASE_MON_DUR[7:0]