IDT 8A3 Series - STATUS.DPLL2_PHASE_STATUS; STATUS.DPLL3_PHASE_STATUS

93©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
STATUS.DPLL2_PHASE_STATUS
Phase offset at output of decimator.
STATUS.DPLL3_PHASE_STATUS
Phase offset at output of decimator.
Table 105: STATUS.DPLL2_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL2_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
0ECh DPLL2_PHASE_STATUS[7:0]
0EDh DPLL2_PHASE_STATUS[15:8]
0EEh DPLL2_PHASE_STATUS[23:16]
0EFh DPLL2_PHASE_STATUS[31:24]
0F0h RESERVED[39:36] DPLL2_PHASE_STATUS[35:32]
STATUS.DPLL2_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL2_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.
Table 106: STATUS.DPLL3_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL3_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
0F4h DPLL3_PHASE_STATUS[7:0]
0F5h DPLL3_PHASE_STATUS[15:8]
0F6h DPLL3_PHASE_STATUS[23:16]
0F7h DPLL3_PHASE_STATUS[31:24]
0F8h RESERVED[39:36] DPLL3_PHASE_STATUS[35:32]
STATUS.DPLL3_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL3_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.