IDT 8A3 Series - STATUS.DPLL4_PHASE_STATUS; STATUS.DPLL5_PHASE_STATUS

94©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
STATUS.DPLL4_PHASE_STATUS
Phase offset at output of decimator.
STATUS.DPLL5_PHASE_STATUS
Phase offset at output of decimator.
Table 107: STATUS.DPLL4_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL4_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
0FCh DPLL4_PHASE_STATUS[7:0]
0FDh DPLL4_PHASE_STATUS[15:8]
0FEh DPLL4_PHASE_STATUS[23:16]
0FFh DPLL4_PHASE_STATUS[31:24]
100h RESERVED[39:36] DPLL4_PHASE_STATUS[35:32]
STATUS.DPLL4_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL4_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.
Table 108: STATUS.DPLL5_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL5_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
104h DPLL5_PHASE_STATUS[7:0]
105h DPLL5_PHASE_STATUS[15:8]
106h DPLL5_PHASE_STATUS[23:16]
107h DPLL5_PHASE_STATUS[31:24]
108h RESERVED[39:36] DPLL5_PHASE_STATUS[35:32]
STATUS.DPLL5_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL5_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.