IDT 8A3 Series - STATUS.DPLL6_PHASE_STATUS; STATUS.DPLL7_PHASE_STATUS

95©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
STATUS.DPLL6_PHASE_STATUS
Phase offset at output of decimator.
STATUS.DPLL7_PHASE_STATUS
Phase offset at output of decimator.
Table 109: STATUS.DPLL6_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL6_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
10Ch DPLL6_PHASE_STATUS[7:0]
10Dh DPLL6_PHASE_STATUS[15:8]
10Eh DPLL6_PHASE_STATUS[23:16]
10Fh DPLL6_PHASE_STATUS[31:24]
110h RESERVED[39:36] DPLL6_PHASE_STATUS[35:32]
STATUS.DPLL6_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL6_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.
Table 110: STATUS.DPLL7_PHASE_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL7_PHASE_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
114h DPLL7_PHASE_STATUS[7:0]
115h DPLL7_PHASE_STATUS[15:8]
116h DPLL7_PHASE_STATUS[23:16]
117h DPLL7_PHASE_STATUS[31:24]
118h RESERVED[39:36] DPLL7_PHASE_STATUS[35:32]
STATUS.DPLL7_PHASE_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
DPLL7_PHASE_STATUS[
35:0]
R/O 0 Signed 36-bit phase offset in ITDC_UIs.