IDT 8A3 Series - Module: PWM_DECODER_0; PWM_DECODER_0.PWM_DECODER_CNFG

261©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
Module: PWM_DECODER_0
Configure PWM decoder.
PWM_DECODER_0.PWM_DECODER_CNFG
Set the rate of the PWM PPS frames and enable the internal PWM PPS signal.
PWM_ENCODER_0.PWM_ENCODER_CMD Bit Field Descriptions
Bit Field Name Field Type Default Value Description
RESERVED N/A - This field must not be modified from the read value
TOD_TX[2] R/W 0 Enable TOD transmission.
The TOD transmission can be enabled only if signature mode is disabled.
0 = disabled
1 = enabled
SIGNATURE_MODE[1] R/W 0 Enable signature mode.
0 = disabled
1 = enabled
ENABLE[0] R/W 0 Enable PWM encoder.
0 = disabled
1 = enabled
Table 344: PWM_DECODER_0 Register Index
Offset
(Hex)
Register Module Base Address: CB40h
a
a. This register module is instantiated multiple times. This is the base address of the first instantiation of this module. For later instantiations,
use the appropriate module base address.
Individual Register Name Register Description
000h PWM_DECODER_0.PWM_DECODER_CNFG PWM_PPS configuration.
002h PWM_DECODER_0.PWM_DECODER_ID PWM decoder identifier.
003h PWM_DECODER_0.PWM_DECODER_SIGNA
TURE_0
PWM decoder signature configuration.
004h PWM_DECODER_0.PWM_DECODER_SIGNA
TURE_1
PWM decoder signature configuration.
005h PWM_DECODER_0.PWM_DECODER_CMD PWM decoder command.
Table 345: PWM_DECODER_0.PWM_DECODER_CNFG Bit Field Locations and Descriptions
Offset
Address
(Hex)
PWM_DECODER_0.PWM_DECODER_CNFG Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
000h PPS_RATE[7:0]
001h GENERATE_
PPS[15]
PPS_RATE[14:8]