142©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
DPLL_0.DPLL_DCO_INC_DEC_SIZE
Configure frequency step size for GPIO increment/decrement mode.
028h DPLL_0.DPLL_FASTLOCK_FSL Fast lock frequency slope limit.
02Ah DPLL_0.DPLL_FASTLOCK_BW Fast lock loop filter bandwidth.
02Ch DPLL_0.DPLL_WRITE_FREQ_TIMER Write frequency timer.
02Eh DPLL_0.DPLL_WRITE_PHASE_TIMER Write phase timer.
030h DPLL_0.DPLL_PRED_CFG Predefined configuration selection.
031h DPLL_0.DPLL_TOD_SYNC_CFG DPLL ToD synchronization configuration.
032h DPLL_0.DPLL_COMBO_SLAVE_CFG_0 Combo mode slave primary source configuration.
033h DPLL_0.DPLL_COMBO_SLAVE_CFG_1 Combo mode slave secondary source configuration.
034h DPLL_0.DPLL_SLAVE_REF_CFG Slave mode configuration.
035h DPLL_0.DPLL_REF_MODE Reference selection configuration.
036h DPLL_0.DPLL_PHASE_MEASUREMENT_CFG Phase measurement mode configuration.
037h DPLL_0.DPLL_MODE DPLL operating modes.
a. This register module is instantiated multiple times. This is the base address of the first instantiation of this module. For later instantiations,
use the appropriate module base address.
Table 173: DPLL_0.DPLL_DCO_INC_DEC_SIZE Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_0.DPLL_DCO_INC_DEC_SIZE Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
000h DCO_INC_DEC_SIZE[7:0]
001h DCO_INC_DEC_SIZE[15:8]
DPLL_0.DPLL_DCO_INC_DEC_SIZE Bit Field Descriptions
Bit Field Name Field Type Default Value Description
DCO_INC_DEC_SIZE[15:
0]
R/W 0 Size of frequency increment/decrement in 0.01 ppb.
Unsigned 16-bit.
0 means no change.
GPIO increment/decrement mode is by setting
GPIO_n.GPIO_CTRL.GPIO_FUNCTION = 0x4 increment / 0x5 decrement.
The DPLL to increment/decrement is configured in
GPIO_n.GPIO_DCO_INC_DEC.DPLL_INDEX.
Table 172: DPLL_0 Register Index
Offset
(Hex)
Register Module Base Address: C3B0h
a
Individual Register Name Register Description
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