IDT 8A3 Series - DPLL_CTRL_0.DPLL_PRED0_PSL; DPLL_CTRL_0.DPLL_PRED1_DAMPING

210©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
DPLL_CTRL_0.DPLL_PRED0_PSL
Predefined configuration 0 loop filter phase slope limit.
DPLL_CTRL_0.DPLL_PRED1_DAMPING
Predefined configuration 1 loop filter damping factor.
DPLL_CTRL_0.DPLL_PRED0_BW Bit Field Descriptions
Bit Field Name Field Type Default Value Description
BW_UNIT[15:14] R/W 0 DPLL loop filter bandwidth unit.
0 = uHz
1 = mHz
2 = Hz
3 = kHz
DPLL_PRED0_BW[13:0] R/W 0 Unsigned 14-bit DPLL loop filter bandwidth value.
Table 260: DPLL_CTRL_0.DPLL_PRED0_PSL Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_CTRL_0.DPLL_PRED0_PSL Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
00Ch DPLL_PRED0_PSL[7:0]
00Dh DPLL_PRED0_PSL[15:8]
DPLL_CTRL_0.DPLL_PRED0_PSL Bit Field Descriptions
Bit Field Name Field Type Default Value Description
DPLL_PRED0_PSL[15:0] R/W 0 Unsigned 16-bit loop filter phase slope limit in ns/s.
Value 0 implies no phase slope limit.
Table 261: DPLL_CTRL_0.DPLL_PRED1_DAMPING Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_CTRL_0.DPLL_PRED1_DAMPING Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
00Eh RESERVED[7:4] DAMP_FTR[3:0]