IDT 8A3 Series - STATUS.DPLL1_FILTER_STATUS; STATUS.DPLL2_FILTER_STATUS

71©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
STATUS.DPLL1_FILTER_STATUS
DPLL 1 loop filter status.
STATUS.DPLL2_FILTER_STATUS
DPLL 2 loop filter status.
Table 68: STATUS.DPLL1_FILTER_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL1_FILTER_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
04Ch FILTER_STATUS[7:0]
04Dh FILTER_STATUS[15:8]
04Eh FILTER_STATUS[23:16]
04Fh FILTER_STATUS[31:24]
050h FILTER_STATUS[39:32]
051h FILTER_STATUS[47:40]
STATUS.DPLL1_FILTER_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.
Fine phase measurement in units of 50/128 picoseconds.
Table 69: STATUS.DPLL2_FILTER_STATUS Bit Field Locations and Descriptions
Offset
Address
(Hex)
STATUS.DPLL2_FILTER_STATUS Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
054h FILTER_STATUS[7:0]
055h FILTER_STATUS[15:8]
056h FILTER_STATUS[23:16]
057h FILTER_STATUS[31:24]
058h FILTER_STATUS[39:32]
059h FILTER_STATUS[47:40]
STATUS.DPLL2_FILTER_STATUS Bit Field Descriptions
Bit Field Name Field Type Default Value Description
FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.
Fine phase measurement in units of 50/128 picoseconds.