Keysight N9010A EXA Service Guide 293
Analog/Digital IF Troubleshooting
40 MHz BW IF Section
Reconstruction
Analog data from the digital FPGA, T2, is fed into a DAC that recreates an
analog signal. It can be either video or the demodulated audio. The signal
can be routed to the analyzer’s audio system (to listen to the demodulated
signals) or to the ANALOG OUT connector on the rear panel.
Clock Distribution
The 100 MHz reference from the A16 Reference Assembly feeds a power
divider. One output of the divider is buffered, doubled, and filtered to
generate the 200 MHz clock needed for ADC2, the ADC for the 40 MHz BW
path,. The remaining output of the power divider is attenuated and buffered
before being fed to the clock distribution IC. This IC generates all the other
clocks needed by the A3 Digital I.F. Assembly as well as the 10 MHz OUT
connector on the rear panel.
Noise Source Voltage Regulator
Various external noise sources can be connected to the rear panel of the
analyzer. These noise sources require a very accurate 28 volt DC power
supply.
The 28 volt BNC output connector is used with the 346 series noise sources.
The Smart Noise Source (SNS) interface includes power switching for the
28 volt and 15 volt power supply. In addition, it has buffers to interface to
the SNS I2C bus for control and read back of ENR data automatically. The
SNS connector is used with the SNS series noise sources.
Digital Bus Common Mode Filtering
The Digital Bus is a real time digital interface. It is sometimes referred to as
Messenger or LVDS. The implementation on the Digital IF is unidirectional,
meaning it can only source data, not receive it. Common mode filtering is
required to translate the digital ground referenced signals to analog ground
at the rear panel.
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