Raven Interrupt Controller Implementation
http://www.motorola.com/computer/literature 2-47
2
PCI I/O CONFIG_DATA Register
If the CONFIG_ADDRESS register is initialized for a PCI Configuration
cycle, an access to the CONFIG_DATA register will write to or read from
a PCI configuration space location. If the CONFIG_ADDRESS register is
initialized for a PCI Special cycle, a word write to the CONFIG_DATA
register will generate a special cycle on the PCI bus.
Raven Interrupt Controller Implementation
Introduction
The Raven Interrupt Controller (Raven MPIC) Features
❏ MPIC programming model
❏ Support for two processors
❏ Support for 16 external interrupts
❏ Support for 15 programmable Interrupt & Processor Task priority
levels
❏ Support for the connection of an external 8259 for ISA/AT
compatibility
❏ Distributed interrupt delivery for external I/O interrupts
❏ Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
Offset $CFC
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name CONFIG_DATA
Operation R/W
Reset $00000000
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