Raven Interrupt Controller Implementation
http://www.motorola.com/computer/literature 2-63
2
Vendor Identification Register
There are two fields in the Vendor Identification Register which are not
defined for the Raven MPIC implementation but are defined in the MPIC
specification. They are the vendor identification and device ID fields.
STP STEPPING.The stepping or silicon revision number is initially 0.
Processor Init Register
P1 PROCESSOR 1. Writing a 1 to P1 will assert the Soft Reset input of
processor 1. Writing a 0 to it will negate the SRESET signal.
P0 PROCESSOR 0. Writing a 1 to P0 will assert the Soft Reset input of
processor 0. Writing a 0 to it will negate the SRESET signal.
The Soft Reset input to the 604 is negative edge-sensitive.
Offset $01080
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name VENDOR IDENTIFICATION
STP
Operation RRRR
Reset $00 $02 $00 $00
Offset $01090
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name PROCESSOR INIT
P1
P0
Operation RRRR
R/W
R/W
Reset $00 $00 $00 $00
0
0
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