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Board Description and Memory Maps
1
System External Cache Control Register (SXCCR)
The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:
SXC_DIS_ System External Cache Enable. When this bit is cleared, it
disables this cache from responding to any bus cycles.
SXC_FLSH_ System External Cache Flush. When this bit is pulsed true
for at least 8 clock periods, it causes the system external cache to write
back dirty cache lines out to system memory and clears all the tag valid
bits.
Flash Size FLSHP0_ FLSHP1_ FLSHP2_
1MB000
2MB001
4MB010
8MB011
16MB 1 0 0
32MB 1 0 1
64MB 1 1 0
No Flash 1 1 1
Register System External Cache Control Register - $FEF88000
Bit 01234567
Field
SXC_DIS_
SXC_RST_
SXC_MI_
SXC_FLSH_
Operation R/W
Reset 1 1 1 1XXXX
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