3-8 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in the 1st beat
column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter..
4-Beat Write after 4-Beat Write
(Quad-word aligned)
10/6
1
11113/9
1-Beat Read after Idle
10 - - -
10
1-Beat Read after 1-Beat Read
11/7
1
---
11/7
1-Beat Write after Idle
4
-
--
4
1-Beat Write after 1-Beat Write
15/11
1
- - - 15/11
Table 3-2. PowerPC 60x Bus to DRAM Access Timing when Configured for
60ns Fast Page Devices
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-word
aligned)
91 2113
4-Beat Read after Idle (Quad-word
misaligned)
931114
4-Beat Read after 4-Beat Read
(Quad-word aligned)
7/3
1
1 2 1 11/7
4-Beat Read after 4-Beat Read
(misaligned)
6/2
1
31111/7
Table 3-1. PowerPC 60x Bus to DRAM Access Timing when Configured for
70ns Fast Page Devices (Continued)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
To Next Page
Loading...
Need help?
General
