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Programming Details
4
Raven MPIC
The Raven ASIC has a built-in interrupt controller that meets the Multi-
Processor Interrupt Controller (MPIC) Specification. This MPIC supports
up to two processors and 16 external interrupt sources. There are also six
other interrupt sources inside the MPIC: two cross-processor interrupts
and four timer interrupts. All ISA interrupts go through the 8259 pair in the
PIB. The output of the PIB then goes through the MPIC in the Raven.
Refer to Chapter 2, Raven PCI Host Bridge & Multi-Processor Interrupt
Controller, for details on the Raven MPIC. The following table shows the
interrupt assignments for the Raven MPIC on the MTX series:
Table 4-3. Raven MPIC Interrupt Assignments
MPIC
IRQ
Edge/
Level
Polarity Interrupt Source Notes
IRQ0 Level High PIB (8259) 1
IRQ1 Edge Low Falcon-ECC Error 2
IRQ2 Level Low PCI-Ethernet 3
IRQ3 Level Low PCI-SCSI 3
IRQ4 Level Low Reserved
IRQ5 Level Low Reserved
IRQ6 Level Low Reserved
IRQ7 Level Low Reserved
IRQ8 Level Low Reserved
IRQ9 Level Low PCI/PMC1 INTA#, PCI/PMC2 INTD#,PCI3
INTC#
3
IRQ10 Level Low PCI/PMC1 INTB#, PCI/PMC2 INTA#, PCI3
INTD#
IRQ11 Level Low PCI/PMC1 INTC#, PCI/PMC2 INTB, PCI3 INTA#
IRQ12 Level Low PCI/PMC1 INTD#, PCI/PMC2 INTC#, PCI3
INTB#
IRQ13 Level Low Not Used
IRQ14 Level Low Not Used
IRQ15 N/A N/A Not Used
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