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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
When PPC Devices are Little-Endian
When all PPC devices are operating in little-endian mode, the PPC address
must be modified to remove the exclusive-ORing applied by PPC60x
processors before being passed on to PCI. The three low order processor
bus address bits are exclusive-ORed with a three-bit value that depends on
the length of the operand, as shown in Table 2-4.
Note The only legal data lengths supported in little-endian mode are 1,
2, 4, or 8-byte aligned transfers.
Cycles Originating From PCI
For bus cycles initiated by PCI masters, the PCI address will be modified
the same way the MCP60x processor does in little-endian mode. The
modification will be the same as that described in the section above. Since
this method has some difficulties dealing with unaligned transfers, the
Raven will break up all unaligned PCI transfers into multiple aligned
transfers on the PPC bus.
Error Handling
The Raven will be capable of detecting and reporting the following errors
to one or more PPC masters:
❏ PPC address bus time-out
❏ PCI master signalled master abort
❏ PCI master received target abort
Table 2-4. Address Modification for Little-Endian Transfers
Data Length (bytes) Address Modification
1 XOR with 111
2XOR with 110
4 XOR with 100
8 no change
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