Registers
http://www.motorola.com/computer/literature 2-45
2
PCIOFFx PCI Slave Offset. This register contains a 16-bit offset that is
added to the upper 16 bits of the PCI address to determine the PPC address
used for transfers from PCI to the PPC bus. This offset allows PPC
resources to reside at addresses that would not normally be visible from
PCI.
CONFIG_ADDRESS
The routing of the PPC data bus to and from the CONFIG_ADDRESS
register depends on the endian bit setting. Refer to the sections on Endian
Conversion, and the LEND bit in the GCSR. The following register
diagrams have two additional rows of information. These rows indicate the
source bit positions on the PPC data bus when data is written to this
register. A read from the CONFIG_ADDRESS register will return
contents to these locations. One row defines the source for big-endian
operation and the second is for little-endian operation. LEND is the little-
endian control bit in the GCSR.
The MSADD3, MSOFF3, and MSATT3 are initialized at reset so software
can access PCI configuration address and data space without changing
Raven registers.
PCI I/O CONFIG_ADDRESS Register
Offset $CF8
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name CONFIG_ADDRESS
EN
BUS DEV FUN REG
Operation
R/W
R R/W R/W R/W R/W
R
R
Reset
1
$00 $00 $00 $0 $00
0
0
LEND = 0 PPC[39:32] PPC[47:40] PPC[55:48] PPC[63:56]
LEND = 1 PPC[31:24] PPC[23:16] PPC[15:8] PPC[7:0]
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