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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
Generating PCI Memory and I/O Cycles
Each programmable slave may be configured to generate PCI I/O or
memory accesses through the MEM and IOM fields in its Attribute register
as shown below.
The IBM CHRP specification describes two approaches for handling PCI
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the IOM bit is used to select between these two modes whenever
a PCI I/O cycle is to be performed.
When MEM is clear or IOM is clear, the Raven will take the PPC address,
apply the offset specified in the MSOFFx register, and map the result
directly to PCI.
When MEM is clear and IOM is set, the Raven will take the PPC address,
apply the offset specified in the MSOFFx register, and map the result to
PCI as shown in the following figure.
MEM IOM PCI Cycle Type
1xMemory
0 0 Contiguous I/O
0 1 Spread I/O
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