Motorola MTX series Programmer's Reference Guide

1-22 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
P0XC_CFG Processor 0 External Cache Configuration Access Mode.
When this bit is set, it maps the Processor 0’s external cache in
Configuration Access Mode. Refer to the IBM15-C700A SLC User’s
Manual for details.
P0XC_DIS_ Processor 0 External Cache Disable. When this bit is
cleared, it disables this cache from responding to any bus cycles.
Processor 1 External Cache Control Register (P1CCR)
The Processor 1 External Cache Control Register is accessed via the
RD[32:39] data lines of the upper Falcon device. This register is not
implemented for systems without In-line Cache. This 8-bit register is
defined as follows:
P1XC_CFG Processor 1External Cache Configuration Access Mode.
When this bit is set, it maps the Processor 1’s external cache in
Configuration Access Mode. Refer to the IBM15-C700A SLC User’s
Manual for details.
P1XC_DIS_ Processor 1External Cache Disable. When this bit is cleared,
it disables this cache from responding to any bus cycles.
Register Processor 1External Cache Control Register - FEF88200h
Bit 01234567
Field
P1XC_CFG
P1XC_DIS_
Operation R/WR/WR/WR/WR/WR/WR/WR/W
Reset 0 0 0 0XXXX

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English