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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
IO/MEM IO Space Indicator. This bit is hard-wired to a logic one to
indicate PCI I/O space.
RES Reserved. This bit is hard-wired to zero.
IOBA I/O Base Address. These bits define the I/O space base address of
the MPIC control registers. The IOBASE decoder is disabled when the
IOBASE value is zero.
Memory Base Register
This register controls the mapping of the MPIC control registers in PCI
memory space.
IO/MEMIO Space Indicator. This bit is hard-wired to a logic zero to
indicate PCI memory space.
MTYPx Memory Type. These bits are hard-wired to zero to indicate that
the MPIC registers can be located anywhere in the 32-bit address space
PRE Prefetch. This bit is hard-wired to zero to indicate that the MPIC
registers are not prefetchable.
MEMBA Memory Base Address. These bits define the memory space
base address of the MPIC control registers. The MBASE decoder is
disabled when the MBASE value is zero.
Offset $14
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name MEMBASE
MEMBA
PRE
MTYP1
MTYP0
IO/MEM
Operation R/W R
R
R
R
R
Reset $0000 $0000
0
0
0
0
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