3-10 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in 1st beat column
are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
Table 3-3. PowerPC 60x Bus to DRAM Access Timing when Configured for
50ns EDO Devices
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-word
aligned)
81 1111
4-Beat Read after Idle (Quad-word
misaligned)
82 1112
4-Beat Read after 4-Beat Read
(Quad-word aligned)
5/2
1
1 1 1 8/5
4-Beat Read after 4-Beat Read
(misaligned)
4/2
1
2118/6
4-Beat Write after Idle 4 1 1 1 7
4-Beat Write after 4-Beat Write
(Quad-word aligned)
4/3
1
1117/6
1-Beat Read after Idle
8
---8
1-Beat Read after 1-Beat Read
7/5
1
---
7/5
1-Beat Write after Idle
4
---4
1-Beat Write after 1-Beat Write
9/7
1
---9/7
To Next Page
Loading...
Need help?
General
