3-18 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Notes
1. No opportunity for error since no read of DRAM occurs during a
four-beat write.
2. The recommended connection for Falcon is for WE* to connect
from upper Falcon to both upper and lower DRAM’s of banks A and
B and for WE* of lower Falcon to connect to both upper and lower
DRAM’s of banks C and D. With this configuration, the write
portion of single-bit-writes and of scrubs does happen if the double-
bit error is in the lower portion of banks A or B or if it is in the upper
portion of banks C or D
Error Logging
ECC error logging is facilitated by the Falcon because of its internal
latches. When an error (single- or double-bit) occurs in the DRAMs to
which a Falcon is connected, it records the address and syndrome bits
associated with the data in error. Each Falcon performs this logging
function independently of the other. Once a Falcon has logged an error, it
does not log any more until the elog control /status bit has been cleared by
software unless the currently logged error is single-bit and a new, double-
bit error is encountered. The logging of errors that occur during scrub can
be enabled/disabled in software. Refer to the Error Logger Register
section for more information.
ROM/Flash Interface
The Falcon pair provides the interface for two blocks of ROM/Flash. Each
block provides addressing and control for up to 64MB.
Note No ECC error checking is provided for the ROM/Flash.
The ROM/Flash interface allows each block to be individually configured
by jumpers and/or by software as follows:
1. Access for each block is controlled by three software programmable
control register bits: an overall enable, a write enable, and a reset
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