Programming Model
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This duplicating of writes from upper to lower applies to the Falcon’s
internal registers only. No duplication is performed for writes to DRAM,
ROM/Flash, or the External Register set.
Programming Model
CSR Architecture
The CSR (control and status register set) consists of the chip’s internal
register set and its external register set. The base address of the CSR is hard
coded to the address $FEF80000 (or $FEF90000 if the SIO pin is low at
reset).
Accesses to the CSR are mapped differently depending on whether they
are reads or writes. For reads, CSR data read on the upper half of the data
bus comes from the upper Falcon while CSR data read on the lower half of
the data bus comes from the lower Falcon. See the figure below.
Figure 3-4. Data Path for Reads from the Falcon Internal CSRs
Upper FALCON
1903 9609
Upper
Lower FALCON
Data Bus
Lower
Data Bus
CSR CSR
MPC60x Master