Motorola MTX series Programmer's Reference Guide

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
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memory. If interrupts from ISA devices are directly connected to the
Raven MPIC (bypassing the 8259), the device driver interrupt
service routine must read status from the ISA device to ensure
buffers between the device and system memory are flushed.
Reset State
After a power-on reset the Raven MPIC state is:
❏ Current task priority for all CPUs set to 15.
❏ All interrupt source priorities set to zero.
❏ All interrupt source mask bits set to a one.
❏ All interrupt source activity bits cleared.
❏ Processor Init Register is cleared.
❏ All counters stopped and interrupts disabled.
❏ Controller mode set to 8259 pass-through.
Operation
Interprocessor Interrupts
Four interprocessor interrupt (IPI) channels are provided for use by all
processors. During system initialization the IPI vector/priority registers for
each channel should be programmed to set the priority and vector returned
for each IPI event. During system operation a processor may generate an
IPI by writing a destination mask to one of the IPI dispatch registers.
Note that each IPI dispatch register is shared by both processors. Each IPI
dispatch register has two addresses but they are shared by both processors.
That is, there is a total of four IPI dispatch registers in the Raven MPIC.
The IPI mechanism may be used for self interrupts by programming the
dispatch register with the bit mask for the originating processor.

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English