Raven Interrupt Controller Implementation
http://www.motorola.com/computer/literature 2-57
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There is a possibility for a priority tie between the two processors when
resolving external interrupts. In that case the interrupt will be delivered to
processor 0 or processor 1 as determined by the TIE mode bit. This case is
not defined in the above rule set.
MPIC Registers
The following conventions are used in the Raven register charts:
❏ R Read Only field.
❏ R/W Read/Write field.
❏ S Writing a ONE to this field sets this field.
❏ C Writing a ONE to this field clears this field.
Raven MPIC Registers
The Raven MPIC register map is shown in the following table. The Off
field is the address offset from the base address of the Raven MPIC
registers in the MPC-IO or MPC-MEMORY space.
Note This map does not depict linear addressing. The Raven PCI-
SLAVE has two decoders for generating the Raven MPIC select.
These decoders will generate a select and acknowledge all
accesses which are in a reserved 256KB range. If the index into
that 256KB block does not decode a valid Raven MPIC register
address, the logic will return $00000000.
The registers are 8, 16, or 32 bits accessible.
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