3-30 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Register Summary
Table 3-11 shows a summary of the CSR. 
Note The table only shows addresses for accesses to the upper Falcon. 
To get the addresses for accesses to the lower Falcon, add 4 to the 
address shown. Since the only way to write to the lower Falcon’s 
internal register set is to duplicate what is written to the upper 
Falcon, only the addresses shown in the table should be used for 
writes to them. Writes to the external register set are not 
duplicated from upper to lower, so writes to them can be via the 
upper or lower Falcon.
Table 3-11.  Register Summary
BIT # ---->
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FEF80000
VENDID DEVID
FEF80008 REVID
aonly_en
isa_hole
adis
ram fref
ram spd0
ram spd1
chipu
FEF80010
ram a en
RA
M A 
SIZ
ram b en
RA
M B 
SIZ
ram c en
RA
M C 
SIZ
ram d en
RA
M D 
SIZ
FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE
FEF80020 CLK 
FREQUENCY
por
FEF80028
refdis
rwcb
derc
scien
dpien
sien
mien
mcken
FEF80030
elog
escb
esen
embt
esbt
ERROR_SYNDR
OME
esblk0
esblk1
scof
SBE COUNT
FEF80038 ERROR_ADDRESS
FEF80040
scb0
scb1
swen
rtest0
rtest1
rtest2