1-18 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
P0/1STAT Processor 0/1 Status. This field is encoded as follows:
Memory Configuration Register (MEMCR)
The states of the RD[00:31] DRAM data pins, which have weak internal
pull-ups, are latched by the lower Falcon chip at a rising edge of the power-
up reset and stored in this Memory Configuration Register. In the MTX,
SYSXC Value External Look-aside Cache Size
0b0000 to 0b1011 Reserved
0b1100 1MB
0b1101 512KB
0b1110 256KB
0b1111 None
P0/1STAT Value Processor 0/1 Present External In-line Cache Size
0b0000 to 0b0011 Reserved Reserved
0b0100 YES 1MB
0b0101 YES 512KB
0b0110 YES 256KB
0b0111 YES None
0b1000 to 0b1111 NO N/A
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