2-48 Computer Group Literature Center Web Site
Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
❏ Four Interprocessor Interrupt sources
❏ Four timers
❏ Processor initialization control
Architecture
The Raven PCI Slave implements two address decoders for placing the
Raven MPIC registers in PCI IO or PCI Memory space. Access to these
registers require MPC and PCI bus mastership. These accesses include
interrupt and timer initialization and interrupt vector reads.
The Raven MPIC receives interrupt inputs from 16 external sources, four
interprocessor sources, four timer sources, and one Raven internal error
detection source. The externally sourced interrupts 1 through 15 have two
modes of activation: low level or active high positive edge. External
interrupt 0 can be either level or edge activated with either polarity. The
Interprocessor and timers interrupts are event activated.
CSR’s Readability
Unless explicitly specified, all registers are readable and return the last
value written. The exceptions are the IPI dispatch registers and the EOI
registers which return zeros on reads, the interrupt source ACT bit which
returns current interrupt source status, the interrupt acknowledge register
which returns the vector of the highest priority interrupt which is currently
pending, and reserved bits which returns zeros. The interrupt acknowledge
register is also the only register which exhibits any read side-effects.
Interrupt Source Priority
Each interrupt source is assigned a priority value in the range from 0 to 15
where 15 is the highest. In order for delivery of an interrupt to take place
the priority of the source must be greater than that of the destination
processor. Therefore setting a source priority to zero inhibits that interrupt.
To Next Page
Loading...
Need help?
General
