Functional Description
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multiplexes it with half of the DRAM data bus. Each Falcon connects to
64 DRAM data-bits and to 8 DRAM check-bits. The total DRAM array
width is 144 bits (2*[64+8]).
Cycle Types
To support ECC, the Falcon pair always deals with DRAM using full
width (144-bit) accesses. When the PowerPC 60x bus master requests any
size read of DRAM, the Falcon pair reads 144 bits at least once. When the
PowerPC 60x bus master requests a four-beat write to DRAM, the Falcon
pair writes all 144 bits twice. When the PowerPC 60x bus master requests
a single-beat write to DRAM, the Falcon pair performs a 144-bit wide read
cycle to DRAM, merges in the appropriate PowerPC 60x bus write data,
and writes 144 bits back to DRAM.
Error Reporting
The Falcon pair checks data from the DRAM during single- and four-beat
reads, during single-beat writes, and during scrubs. Table 3-8 shows the
actions it takes for different errors during these accesses.
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