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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
DPAR Data Parity Detected. This bit is set when three conditions are
met: 1) the Raven asserted PERR* itself or observed PERR* asserted; 2)
the Raven was the PCI master for the transfer in which the error occurred;
3) the PERR bit in the PCI Command Register is set. This bit is cleared by
writing it to 1; writing a 0 has no effect.
SELTIM DEVSEL Timing. This field indicates that the Raven will
always assert DEVSEL* as a ‘medium’ responder.
SIGTA Signalled Target Abort. This bit is set by the PCI slave
whenever it terminates a transaction with a target-abort. It is cleared by
writing it to 1; writing a 0 has no effect.
RCVTA Received Target Abort. This bit is set by the PCI master
whenever its transaction is terminated by a target-abort. It is cleared by
writing it to 1; writing a 0 has no effect.
RCVMA Received Master Abort. This bit is set by the PCI master
whenever its transaction (except for Special Cycles) is terminated by a
master-abort. It is cleared by writing it to 1; writing a 0 has no effect.
SIGSE Signaled System Error. This bit is set whenever the Raven
asserts SERR*. It is cleared by writing it to 1; writing a 0 has no effect.
RCVPE Detected Parity Error. This bit is set whenever the Raven
detects a parity error, even if parity error checking is disabled (see bit
PERR in the PCI Command Register). It is cleared by writing it to 1;
writing a 0 has no effect.
Revision ID/ Class Code Registers
REVID Revision ID. This register identifies the Raven revision level.
This register is duplicated in the PPC Registers.
Offset $08
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name CLASS REVID
Operation RR
Reset $060000 $03
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