Interrupt Handling
http://www.motorola.com/computer/literature 4-5
4
Notes
1. Interrupt from the PCI/ISA Bridge.
2. Interrupt from the Falcon chipset for a Single and/or Double bit
memory error.
3. These interrupts also appear at the PIB for backward compatibility
with older MVME1600 and PM603/4 modules.
8259 Interrupts
There are 15 interrupt requests supported by the PIB. These 15 interrupts
are ISA-type interrupts that are functionally equivalent to two 82C59
interrupt controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13,
each of the interrupt lines can be configured for either edge-sensitive mode
or level-sensitive mode by programming the appropriate ELCR registers
in the PIB.
There is also support for four PCI interrupts, PIRQ3_-PIRQ0_. The PIB
has four PIRQ Route Control Registers to allow each of the PCI interrupt
lines to be routed to any of eleven ISA interrupt lines (IRQ0, IRQ1, IRQ2,
IRQ8_, and IRQ13 are reserved for ISA system interrupts). Since PCI
interrupts are defined as level-sensitive, software must program the
selected IRQ(s) for level-sensitive mode. Note that more than one PCI
interrupt can be routed to the same ISA IRQ line. The PIB can be
programmed to handle the PCI interrupts if the Raven MPIC is either not
present or not used.
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