Motorola MTX series Programmer's Reference Guide

3-58 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Note For descriptions of how these registers are used in the PowerPC
series boards, refer to the Falcon-Controlled System Registers on
page 1-16, especially the System External Cache Control
Register (SXCCR) on page 1-20 and the CPU Control Register on
page 1-23.
Software Considerations
This section contains information that will be useful in programming a
system that uses the Falcon pair.
Parity Checking on the PowerPC Bus
The Falcon does not generate parity on the PowerPC address bus. Because
of this, the appropriate registers in the MPC60x should not be programmed
to enable parity checking for the address bus.
The Falcon does generate parity on the PowerPC data bus. The appropriate
registers in the MPC60x can be programmed to enable parity checking for
the data bus.
Programming ROM/Flash Devices
Those who program devices to be controlled by the Falcon should make
note of the address mapping that is shown in Table 3-9 and in Table 3-10.
For example, when using 8-bit devices, the code will be split so that every
other 4-byte segment goes in each device.
Writing to the Control Registers
Software should not change control register bits that affect DRAM
operation while DRAM is being accessed. Because of pipelining, software
should always make sure that the two accesses before and after the
updating of critical bits are not DRAM accesses. A possible scenario for
trouble would be to execute code out of DRAM while updating the critical

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English