Motorola MTX series Programmer's Reference Guide

Programming Model
http://www.motorola.com/computer/literature 1-15
1
The maximum size of each DRAM block is 1GB.
Falcon Chipset
The Falcon chipset consists of two identical Falcon ASIC devices; The
upper Falcon and the lower Falcon. The upper Falcon connects to the
upper half of the system data bus, DH00 through DH31, while the lower
Falcon connects to lower half of the system data bus, DL00 through DL31.
Table 1-12. Typical DIMM SPD Information
Byte# Value
(hex)
Entry
Value
Description
0 0hxx x Number of SPD bytes
1 0h08 256 Total # bytes in SPD EEPROM
2 0h01
0h02
Fast Page
EDO
Memory type
3 oh0C 12 # of row addresses
4 0h0B 11 # of column addresses
5 0h01 1 # of banks/DIMM
6 0h40
0h48
x64
x72
Module data width
7 0h00 0 Module data width (cont.)
8 0h01 LVTTL Module interface levels
9 0h3C
0h46
60ns
70ns
RAS access time
10 0h0F
0h14
15ns
20ns
CAS access time
11 0h00
0h02
None
ECC
Error detect/correction
configuration
12 0h00 15.6 us Normal Refresh rate/type
13 0h08 x8 Primary DRAM organization
14 0h00 Undefined Secondary DRAM organization

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English