Raven Interrupt Controller Implementation
http://www.motorola.com/computer/literature 2-73
2
Note Each IPI Dispatch Register has two addresses. These registers are
considered to be per processor registers and there is one address
per processor. Reading these registers returns zeros.
P1 PROCESSOR 1. The interrupt is directed to processor 1.
P0 PROCESSOR 0. The interrupt is directed to processor 0.
Interrupt Task Priority Registers
There is one Task Priority Register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority Register to
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset or when the Init bit associated with this processor is
written to a one.
Interrupt Acknowledge Registers
Offset Processor 0 $20080
Processor 1 $21080
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name INTERRUPT TASK PRIORITY
TP
Operation RRRRR/W
Reset $00 $00 $00 $0 $F
Offset Processor 0 $200A0
Processor 1 $210A0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name VECTOR
Operation RRRR
Reset $00 $00 $00 $FF
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