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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
transaction. This signal will remain asserted until the PPC bound
FIFO count has reached zero.
The PPC slave address decode logic settles out several clocks after
the assertion of TS*, at which time the PPC slave can determine the
transaction type. If it is a read and PPCFBR is enabled, the PPC
slave will look at the pcis_fbrabt signal. If this signal is active, the
PPC slave will retry the processor.
When the PCIFBR bit is set, Raven will handle read transactions
originating from the PCI bus in the following manner:
❏ Write posted transactions originating from the PCI bus are flushed
by the nature of the FIFO architecture. The Raven will hold the PCI
master with wait states until the PPC bound FIFO is empty.
❏ Write posted transactions originated from the PPC bus are flushed
in the following manner. The PPC slave will set a signal called
ppcs_fbrabt anytime it has committed to performing a posted write
transaction. This signal will remain asserted until the PCI bound
FIFO count has reached zero.
The PCI slave decode logic settles out several clocks after the
assertion of FRAME*, at which time the PCI slave can determine
the transaction type. If it is a read and PCIFBR is enabled, the PCI
slave will look at the ppcs_fbrabt signal. If this signal is active, the
PCI slave will retry the PCI master.
Registers
This chapter provides a detailed description of all Raven registers. The
Raven ASIC functions as the PPC to PCI Host Bridge. It also contains an
interrupt controller, the Raven MPIC. The Raven ASIC has three sets of
registers: The PPC Register set, the PCI Configuration Register set, and
the Raven MPIC Register set. The PPC Registers are described first; the
PCI Configuration Registers next, and the MPIC Register set last.
The following conventions are used in the Raven register charts:
❏ R Read Only field.
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