Functional Description
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posted write transaction, the transaction will be terminated with a retry.
Note that a mod-4 non-posted write transaction could be interrupted
between write cycles, and thereby result in a partially completed write
cycle. It is recommended that write cycles to write-sensitive non-posted
locations be performed on mod-4 address boundaries.
The Raven has a programmable option to guarantee all PCI write posted
transactions are completed before an PPC initiated read transaction may be
allowed to complete. This option is controlled by the FLBRD bit in the
GSCR register. If this bit is set, all PPC read transactions will be retried
until all posted PCI write transactions have completed. It is recommended
that this option be disabled, and the FLBRD bit be left in the default
(disabled) state.
Transaction Ordering
The PCI Local Bus Specification 2.0, listed in Appendix A, Related
Documentation, states that posted write buffers in both directions must be
flushed before completing a read in either direction. Raven supports this
by providing two optional FIFO flushing options. The PPCFBR (PPC
Flush Before Read) bit within the GCSR register controls the flushing of
PCI write posted data when performing PPC originated read transactions.
The PCIFBR bit within the GCSR register controls the flushing of PPC
write posted data when performing PCI originated read transactions. The
PCIFBR and PPCFBR functions are completely independent of each
other, however both functions must be enabled to guarantee full
compliance with PCI Local Bus Specification 2.0, Appendix A, Related
Documentation.
When the PPCFBR bit is set, Raven will handle read transactions
originating from the PPC bus in the following manner:
❏ Write posted transactions originating from the processor bus are
flushed by the nature of the FIFO architecture. The Raven will hold
the processor with wait states until the PCI bound FIFO is empty.
❏ Write posted transactions originated from the PCI bus are flushed in
the following manner. The PCI slave sets a signal called
‘pcis_fbrabt’ anytime it has committed to performing a posted write
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