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Falcon ECC Memory Controller Chip Set

PowerPC 60x Bus Interface

The Falcon pair has a PowerPC slave interface only. It has no PowerPC

master interface. The slave interface is the mechanism for all accesses to

DRAM, ROM/Flash, and internal and external register sets.

Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing when configured

for 75ns Devices

ACCESS TYPE CLOCK PERIODS REQUIRED FOR: Total

Clocks

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

4-Beat Read 40 13 36 9 36 9 36 9 148 40

4-Beat Write N/A N/A

1-Beat Read (1 byte) 1313------1313

1-Beat Read (2 to 8

bytes)

4013------4013

1-Beat Write 1919------1919

Table 3-7. PowerPC 60x Bus to ROM/Flash Access Timing when configured

for 45ns Devices

ACCESS TYPE CLOCK PERIODS REQUIRED FOR: Total

Clocks

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

4-Beat Read 32 11 28 7 28 7 28 7 116 32

4-Beat Write N/A N/A

1-Beat Read (1 byte) 1111------1111

1-Beat Read (2 to 8

bytes)

3211------3211

1-Beat Write 1919------1919

Motorola MTX series Programmer's Reference Guide

Other manuals for Motorola MTX series