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Falcon ECC Memory Controller Chip Set
3
For writes, internal register data written on the upper half of the data bus
goes to the upper Falcon and is automatically copied by hardware to the
lower Falcon. Internal register data written on the lower half of the data bus
does not go to either Falcon in the pair, but the access is terminated
normally with TA_. See the figure below.
Figure 3-5. Data Path for Writes to the Falcon Internal CSRs
External register data that is written on the upper data bus goes through the
upper Falcon, while data that is written on the lower data bus goes through
the lower Falcon. Unlike the internal register set, there is no automatic
copying of upper data to lower data for the external register set.
CSR read accesses can have a size of 1, 2, 4, or 8 bytes with any alignment.
CSR write accesses are restricted to a size of 1 or 4 bytes and they must be
aligned. Figure 3-6, Figure 3-7, Figure 3-8, and Figure 3-9 show the
memory maps for the different kinds of access.
Upper FALCON
1904 9609
Upper
Data Bus
Lower
Data Bus
CSR
MPC60x Master
Lower FALCON
CSR
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