Raven Interrupt Controller Implementation
http://www.motorola.com/computer/literature 2-61
2
Feature Reporting Register
NIRQ NUMBER OF IRQs. The number of the highest external IRQ
source supported. The IPI, Timer, and Raven Detected Error interrupts are
excluded from this count.
NCPU NUMBER OF CPUs. The number of the highest physical CPU
supported. There are two CPUs supported by this design. CPU #0 and CPU
#1.
VID VERSION ID. Version ID for this interrupt controller. This value
reports what level of the specification is supported by this implementation.
Version level of 03 is used for this release of the MPIC specification.
Global Configuration Register
Offset $01000
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name FEATURE REPORTING
NIRQ NCPU VID
Operatio
n
RRRRR
Reset $0 $00F $0 $01 $03
Offset $01020
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name GLOBAL CONFIGURATION
RESET
M
T
Operation
C
R
R/W
R/W
RRRR
Reset
0
0
0
$0
$00 $00 $00 $00
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