Motorola MTX series Programmer's Reference Guide

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
RTA PCI Master Received Target Abort. This bit is set when the PCI
master receives target abort to terminate a PCI transaction. It may be
cleared by writing it to a 1; writing it to a 0 has no effect. When the RTAM
bit in the ERREN register is set, the assertion of this bit will assert MCHK
to the master designated by the MID field in the ERRAT register. When
the RTAI bit in the ERREN register is set, the assertion of this bit will
assert an interrupt through the OpenPIC interrupt controller.
PPC Error Address Register
EERAD PPC Error Address. This register captures the PPC address
when the PATO bit is set in the EERST register. It captures the PCI address
when the SMA or RTA bits are set in the EERST register. Its contents are
not defined when the PDPE, PERR or SERR bits are set in the EERST
register.
PPC Error Attribute Register - MERAT
If the PDPE, PERR or SERR bits are set in the MERST register, the
contents of the MERAT register are zero. If the MATO bit is set the
register is defined by the following figure:
Address $FEFF0028
Bit
0123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Name EERAD
Operation R
Reset $00000000

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English