Registers
http://www.motorola.com/computer/literature 2-31
2
MIDx PPC Master ID. This field contains the ID of the PPC master
which originated the transfer in which the error occurred. The encoding
scheme is identical to that used in the GCSR register.
TBST* Transfer Burst. This bit is set when the transfer in which the
error occurred was a burst transfer.
TSIZx* Transfer Size. This field contains the transfer size of the PPC
transfer in which the error occurred.
TTx* Transfer Type. This field contains the transfer type of the PPC
transfer in which the error occurred.
* Refer to PowerPC documents listed in Table A-2 on page A-2.
If the SMA or RTA bit are set the register is defined by the following table.
Address $FEFF002C
Bit
0123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Name MERAT
MID1
MID0
TBST
TSIZ0
TSIZ1
TSIZ2
TT0
TT1
TT2
TT3
TT4
Operation RR
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset $00 $00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address $FEFF002C
Bit
0123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Name MERAT
WP
MID1
MID0
COMM3
COMM2
COMM1
COMM0
BYTE7
BYTE6
BYTE5
BYTE4
BYTE3
BYTE2
BYTE1
BYTE0
Operation RR
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset $00 $00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0