2-52 Computer Group Literature Center Web Site
Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
Note Because a deadlock condition can occur when the task register
priorities for each processor are the same and both processors are
targeted for interrupt delivery, the interrupt will be delivered to
processor 0 or processor 1 as determined by the TIE mode.
Block Diagram Description
The description of the block diagram focuses on the theory of operation for
the interrupt delivery logic. If the preceding section is a satisfactory
description of the interrupt delivery modes and the reader is not interested
the logic implementation, this section can be skipped.
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