Motorola MTX series Programmer's Reference Guide

Registers
http://www.motorola.com/computer/literature 2-29
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PATO PPC Address Bus Time-out. This bit is set when the PPC address
bus timer times out. It may be cleared by writing it to a 1; writing it to a 0
has no effect. When the PATOM bit in the ERREN register is set, the
assertion of this bit will assert MCHK to the master designated by the MID
field in the ERRAT register. When the PATOI bit in the ERREN register
is set, the assertion of this bit will assert an interrupt through the MPIC
interrupt controller.
PDPE PPC Data Parity Error. This bit is set when Raven detects a data
bus parity error. This bit is only valid if PPC data bus parity mode is
enabled. It may be cleared by writing it to a 1: writing it to a 0 has no effect.
When the PDPEM bit in the ERREN register is set, the assertion of this bit
will assert MCHK to the master designated by the MID field in the ERRAT
reigster. When the PDPEI bit in the ERREN register is set, the assertion of
this bit will assert an interrupt through the OpenPIC interrupt controller.
PERR PCI Parity Error. This bit is set when the PCI PERR* pin is
asserted. It may be cleared by writing it to a 1; writing it to a 0 has no effect.
When the PERRM bit in the ERREN register is set, the assertion of this bit
will assert MCHK to the master designated by the DFLT bit in the ERRAT
register. When the PERRI bit in the ERREN register is set, the assertion of
this bit will assert an interrupt through the OpenPIC interrupt controller.
SERR PCI System Error. This bit is set when the PCI SERR* pin is
asserted. It may be cleared by writing it to a 1; writing it to a 0 has no effect.
When the SERRM bit in the ERREN register is set, the assertion of this bit
will assert MCHK to the master designated by the DFLT bit in the ERRAT
register. When the SERRI bit in the ERREN register is set, the assertion of
this bit will assert an interrupt through the OpenPIC interrupt controller.
SMA PCI Master Signalled Master Abort. This bit is set when the PCI
master signals master abort to terminate a PCI transaction. It may be
cleared by writing it to a 1; writing it to a 0 has no effect. When the SMAM
bit in the ERREN register is set, the assertion of this bit will assert MCHK
to the master designated by the MID field in the ERRAT register. When
the SMAI bit in the ERREN register is set, the assertion of this bit will
assert an interrupt through the OpenPIC interrupt controller.

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English