Functional Description
http://www.motorola.com/computer/literature 2-17
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❏ PCI parity error
❏ PCI system error
Each of these error conditions will cause an error status bit to be set in the
PPC Error Status Register. If a second error is detected while any of the
error bits is set, the OVFL bit is asserted, but none of the error bits are
changed. Each bit in the PPC Error Status Register may be cleared by
writing a 1 to it; writing a 0 to it has no effect. New error bits may be set
only when all previous error bits have been cleared.
When any bit in the PPC Error Status register is set, the Raven will attempt
to latch as much information as possible about the error in the PPC Error
Address and Attribute Registers. Information is saved as follows:
Each MERST error bit may be programmed to generate a machine check
and/or a standard interrupt. The error response is programmed through the
PPC Error Enable Register on a source by source basis. When a machine
check is enabled, either the MID field in the PPC Error Attribute Register
or the DFLT bit in the MEREN Register determine the master to which the
machine check is directed. For errors in which the master who originated
the transaction can be determined, the MID field is used, provided the MID
is %00 (processor 0), %01 (processor 1), or %10 (processor 2). For errors
not associated with a particular PPC master, or associated with masters
other than processor 0, 1, or 2, the DFLT bit is used. One example of an
error condition which cannot be associated with a particular PPC master
would be a PCI system error.
Error Status Error Address and Attributes
MATO From PPC bus
SMA From PCI bus
RTA From PCI bus
PERR Invalid
SERR Invalid
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