Motorola MTX series Programmer's Reference Guide

3-54 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
software needs to check the status of both upper and lower Data Parity
Error Logger, Address, and Data registers before it clears the dpelog bits.
Otherwise, it could miss a logged error.
dpelog is set when a parity error occurs on the Falcon’s half of the 60x data
bus during any 60x data cycle. It is cleared by writing a one to the upper
Falcon’s dpelog bit or by power-up reset.
dpe_tt is the value that was on the tt0-tt4 signals when the Falcon’s dpelog
bit was set.
dpe_dp is the value that was on the Falcon’s dp0-dp3 signals when its
dpelog bit was set.
When dpe_ckall is set, the Falcon checks data parity on all cycles in which
ta_ is asserted. When dpe_ckall is cleared, the Falcon checks data parity
on cycles when ta_ is asserted only during writes to the Falcon Pair.
Note The Falcon does not check parity during cycles in which there is
a qualified artry_ at the same time as the ta_
When dpe_me is set, the transition of a Falcon’s dpelog bit from false to
true causes it to pulse its machine check interrupt request pin (MCP_) true.
When dpe_me is cleared, the Falcon does not assert its MCP_ pin based
on its dpelog bit.
The GWDP0-7 bits are used to invert the value that is driven onto DP0-
DP7 respectively during reads to the Falcon pair. This allows test software
to generate wrong (even) parity on selected byte lanes. For example, to
create a parity error on the 60x DL24-DL31 and DP7 signals during Falcon
reads, software should set GWDP7.
Note While the value on GWDP is duplicated on both the upper and
lower Falcons, GWDP0-3 affect only the upper Falcon and
GWDP4-7 affect only the lower Falcon.

Motorola MTX series Specifications

General

Brand	Motorola
Model	MTX series
Category	Portable Radio
Language	English