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Motorola MTX series Programmer's Reference Guide
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T
able 3-2
3. PowerP
C Data to DRAM Data Ma
pping (Conti
nued)
PowerPC
DRAM Array
197
199
Table of Contents
Default Chapter
7
Table of Contents
7
About this Manual
17
Summary of Changes
17
Overview of Contents
18
Comments and Suggestions
18
Manual Terminology
19
Conventions Used in this Manual
20
CHAPTER 1 Board Description and
22
Memory Maps
22
Introduction
22
Feature Summary
22
Table 1-1. MTX Series Features Summary
22
System Block Diagram
23
Functional Description
24
Overview
24
Figure 1-1. MTX Series System Block Diagram
25
Programming Model
26
Memory Maps
26
Processor Memory Maps
26
Table 1-2. Default Processor Memory Map
26
Table 1-3. CHRP Memory Map Example
27
Table 1-4. Raven MPC Register Values for CHRP Memory Map
29
Table 1-5. PREP Memory Map Example
29
Table 1-6. Raven MPC Register Values for PREP Memory Map
30
PCI Memory Maps
31
Table 1-7. PCI CHRP Memory Map Example
32
Table 1-8. Raven PCI Register Values for CHRP Memory Map
32
Table 1-10. Raven PCI Register Values for PREP Memory Map
33
Table 1-9. PCI PREP Memory Map
33
MPC System Bus
34
Look-Aside Cache
34
Processor PLL Configuration
34
Processor Type Identification
34
Processors
34
Table 1-11. PVR Values
34
Falcon FLASH Memory
35
System Memory
35
Falcon Chipset
36
Table 1-12. Typical DIMM SPD Information
36
Falcon Registers
37
Falcon-Controlled System Registers
37
Table 1-13. System Register Summary
37
System Configuration Register (SYSCR)
38
Memory Configuration Register (MEMCR)
39
System External Cache Control Register (SXCCR)
41
Processor 0 External Cache Control Register (P0XCCR)
42
Processor 1 External Cache Control Register (P1CCR)
43
CPU Control Register
44
ISA Local Resource Bus
44
W83C553 PIB Registers
44
Primary and Secondary EIDE Ports
44
PC87308VUL Super I/O Strapping
45
NVRAM/RTC & Watchdog Timer Registers
45
Table 1-14. Strap Pins Configuration for the PC87308VUL
45
Table 1-15. MK48T59/559 Access Registers
45
Module Configuration and Status Registers
46
CPU Configuration Register
46
Table 1-16. Module Configuration and Status Registers
46
Base Module Feature Register
47
Base Module Status Register (BMSR)
48
Extended Status Register
48
SCSI Terminator Select
49
Seven-Segment Display Register
50
Z85230 ESCC and Z8536 CIO Registers and Port Pins
50
Z8536/Z85230 Registers
50
Z8536 CIO Port Pins
51
Table 1-17. Z8536/Z85230 Access Registers
51
Table 1-18. Z8536 CIO Port Pins Assignment
51
Table 1-19. I2C Controller Access Registers
52
ISA DMA Channels
53
Table 1-21. PIB DMA Channel Assignments
53
CHAPTER 2 Raven PCI Host Bridge & Multi-Processor Interrupt Controller
54
Introduction
54
Overview
54
Requirements
54
Features
54
Block Diagram
56
Figure 2-1. Raven Block Diagram
56
Functional Description
57
PPC Bus Interface
57
PPC Map Decoders
57
Table 2-1. CHRP Compliant Memory Map
57
PPC Write Posting
58
PPC Master
59
Table 2-2. PPC Transfer Types
61
PPC Bus Timer
62
PCI Interface
62
PCI Map Decoders
62
PCI Configuration Space
63
PCI Write Posting
63
PCI Master
64
Table 2-3. PCI Command Codes
64
Generating PCI Memory and I/O Cycles
65
Generating PCI Configuration Cycles
66
Figure 2-2. PCI Spread I/O Cycle Mapping
66
Generating PCI Special Cycles
67
Generating PCI Interrupt Acknowledge Cycles
67
Endian Conversion
67
Figure 2-3. Big- to Little-Endian Data Swap
68
When PPC Devices Are Big-Endian
68
Table 2-4. Address Modification for Little-Endian Transfers
69
When PPC Devices Are Little-Endian
69
PCI/PPC Contention Handling
71
Transaction Ordering
72
Registers
73
PPC Registers
74
Table 2-5. Raven PPC Register Map
75
Vendor ID/Device ID Registers
75
Revision ID Register
76
Prescaler Adjust Register
78
PPC Error Enable Register
79
PPC Error Status Register
81
PPC Error Address Register
83
PCI Interrupt Acknowledge Register
85
PPC Slave Address (0,1 and 2) Registers
86
PPC Slave Offset/Attribute (0,1 and 2) Registers
87
PPC Slave Offset/Attribute (3) Registers
88
General Purpose Registers
89
PCI Registers
90
Table 2-6. Raven PCI Configuration Register Map
90
Table 2-7. Raven PCI I/O Register Map
91
Vendor ID/ Device ID Registers
91
PCI Command/ Status Registers
92
Revision ID/ Class Code Registers
93
Header Type Register
94
Memory Base Register
95
PCI Slave Address (0,1,2 and 3) Registers
96
PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
97
Config_Address
98
PCI I/O CONFIG_DATA Register
100
Architecture
101
Processor's Current Task Priority
102
Compatibility
103
Interrupt Delivery Modes
104
Block Diagram Description
105
Figure 2-4. Raven MPIC Block Diagram
106
Program Visible Registers
107
Interrupt Request Register (IRR)
108
MPIC Registers
110
Table 2-8. Raven MPIC Register Map
111
Feature Reporting Register
114
Vendor Identification Register
116
IPI Vector/Priority Registers
117
Spurious Vector Register
118
Timer Current Count Registers
119
Timer Vector/Priority Registers
120
Timer Destination Registers
121
External Source Vector/Priority Registers
122
External Source Destination Registers
123
Raven-Detected Errors Vector/Priority Register
124
Raven-Detected Errors Destination Register
125
Interrupt Task Priority Registers
126
End-Of-Interrupt Registers
127
Reset State
129
Dynamically Changing I/O Interrupt Configuration
130
Current Task Priority Level
131
Introduction
132
CHAPTER 3 Falcon ECC Memory Controller Chip Set
133
Block Diagrams
133
Figure 3-1. Falcon Pair Used with DRAM in a System
134
Figure 3-2. Falcon Internal Data Paths (Simplified)
135
Figure 3-3. Overall DRAM Connections
136
Functional Description
137
Single-Beat Reads/Writes
138
Table 3-1. Powerpc 60X Bus to DRAM Access Timing When Configured for 70Ns Fast
138
Table 3-2. Powerpc 60X Bus to DRAM Access Timing When Configured for 60Ns Fast
139
Table 3-3. Powerpc 60X Bus to DRAM Access Timing When Configured for 50Ns EDO Devices
141
Rom/Flash Speeds
142
Table 3-4. Powerpc 60X Bus to Rom/Flash Access Timing When Configured for 180Ns Devices
142
Table 3-5. Powerpc 60X Bus to Rom/Flash Access Timing When Configured for 120Ns Devices
142
Table 3-6. Powerpc 60X Bus to Rom/Flash Access Timing When Configured for 75Ns Devices
143
Table 3-7. Powerpc 60X Bus to Rom/Flash Access Timing When Configured for 45Ns Devices
143
Responding to Address Transfers
144
Cache Coherency
145
Cycle Types
146
Table 3-8. Error Reporting
148
Error Logging
149
Table 3-9. Powerpc 60X to Rom/Flash Address Mapping When Rom/Flash Is
151
Bits Wide (8 Bits Per Falcon)
151
Table 3-10. Powerpc 60X to Rom/Flash Address Mapping When Rom/Flash Is 64 Bits Wide (32 Bits Per Falcon)
152
Refresh/Scrub
153
Blocks a And/Or B Present, Blocks C And/Or D Present
154
Chip Defaults
155
Figure 3-4. Data Path for Reads from the Falcon Internal Csrs
156
Programming Model
156
Figure 3-5. Data Path for Writes to the Falcon Internal Csrs
157
Figure 3-6. Memory Map for Byte Reads to the CSR
158
Figure 3-7. Memory Map for Byte Writes to the Internal Register Set
159
Figure 3-8. Memory Map for 4-Byte Reads to the CSR
160
Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set
160
Table 3-11. Register Summary
161
Detailed Register Bit Descriptions
163
Revision ID/General Control Register
164
Table 3-12. Ram Spd1,Ram Spd0 and DRAM Type
165
DRAM Attributes Register
166
Table 3-13. Block_A/B/C/D Configurations
167
DRAM Base Register
168
ECC Control Register
169
Error Logger Register
172
Error_Address Register
175
Refresh/Scrub Address Register
176
Table 3-14. Rtest Encodings
176
ROM a Base/Size Register
177
Table 3-15. Rom/Flash Block a Size Encoding
178
Table 3-16. Rom_A_Rv and Rom_B_Rv Encoding
179
Table 3-17. Read/Write to Rom/Flash
180
ROM B Base/Size Register
181
Table 3-18. Rom/Flash Block B Size Encoding
182
ROM Speed Control Register
183
Table 3-19. Rom Speed Bit Encodings
183
Data Parity Error Logger Register
184
Data Parity Error Address Register
186
Bit Counter
187
Power-Up Reset Status Register 2
188
Software Considerations
189
Sizing DRAM
190
Table 3-20. Powerpc 60X Address to DRAM Address Mappings
192
Table 3-21. Syndrome Codes Ordered by Bit in Error
193
ECC Codes
193
Table 3-22. Single-Bit Errors Ordered by Syndrome Code
194
Data Paths
195
Figure 3-10. Powerpc Data to DRAM Data Correspondence
196
Table 3-23. Powerpc Data to DRAM Data Mapping
197
Table 4-1. IDSEL Mapping for PCI Devices
199
Introduction
199
Table 4-2. PCI Arbitration Assignments
200
Figure 4-1. MTX Series Interrupt Architecture
201
CHAPTER 4 Programming Details
201
Interrupt Handling
201
Table 4-3. Raven MPIC Interrupt Assignments
202
Interrupts
203
Figure 4-2. PIB Interrupt Handler Block Diagram
204
Table 4-4. PIB PCI/ISA Interrupt Assignments
205
ISA DMA Channels
206
Soft Reset
207
Table 4-5. Reset Sources and Devices Affected
207
Table 4-6. Error Notification and Handling
208
Figure 4-3. Big-Endian Mode
209
Endian Issues
209
Processor/Memory Domain
210
Raven's Involvement
211
Rom/Flash Initialization
212
APPENDIX A Related Documentation
213
Motorola Computer Group Documents
213
Table A-2. Manufacturers' Documents
214
Related Specifications
216
Urls
217
Other manuals for Motorola MTX series
Detailed Service Manual
639 pages
Theory/Troubleshooting Manual
60 pages
Service Manual
146 pages
4
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Motorola MTX series Specifications
General
Brand
Motorola
Model
MTX series
Category
Portable Radio
Language
English
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