2-2 Computer Group Literature Center Web Site
Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2
– 64-bit data bus, 32-bit address bus.
– Optional bus arbitration logic supporting up to three bus masters.
– Four independent software programmable slave map decoders.
– Multi-level write post FIFO for writes to PCI.
– Support for PPC bus clock speeds up to 66 MHz.
– Selectable big or little-endian operation.
❏ PCI Interface
– Fully PCI Rev. 2.0 compliant.
– 32-bit or 64-bit address/data bus.
– Support for accesses to all four PCI address spaces.
– Single-level write posting buffers for writes to the PPC bus.
– Read-ahead buffer for reads from the PPC bus.
– Four independent software programmable slave map decoders.
❏ Interrupt Controller
– MPIC compliant.
– Support for 16 external interrupt sources and two processors.
– Multiprocessor interrupt control allowing any interrupt source to
be directed to either processor.
– Multilevel cross processor interrupt control for multiprocessor
synchronization.
– Four 31 bit tick timers.
❏ Two 64-bit general purpose registers for cross-processor
messaging.
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